This bachelor thesis introduces novel algorithms for the area minimization of Multi-Input And-Inverter Graphs (MAIGs) within the field of logic synthesis. The primary focus is on the implementation of a new method named "Boolean network optimization by stochastic rewiring". This approach significantly diverges from traditional techniques like algebraic factoring and AIG rewriting by adopting a global strategy to add and remove wires at various locations within the
circuit. The method relies on a simple randomization strategy to produce structural variations in the AIGs. Additionally, the thesis formulates and proves a new criterion for acceptable fanins, which ensures valid insertions and deletions without compromising the functionality of the circuit. Experimental results validate the effectiveness of the proposed algorithm in optimizing benchmark circuits. This work is important as it addresses the growing demand for smaller, more efficient circuits in modern electronics, potentially reducing manufacturing costs and enhancing performance.