Boolean network optimization by stochastic rewiring

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dc.contributor.authorCherevko, Christina
dc.date.accessioned2024-06-12T12:52:02Z
dc.date.available2024-06-12T12:52:02Z
dc.date.issued2024
dc.description.abstractIn today’s rapidly evolving technological world, the demand for smaller yet more powerful computers is escalating at an unprecedented pace, driving a significant need for research in circuit optimizations. This surge in demand underscores the critical role of logic synthesis, which lies at the heart of digital circuit design. Logic synthesis serves as a pivotal stage in converting a high-level functionality description into an efficient hardware implementation. It is key to meeting the ever-increasing demands for miniaturization and performance enhancement in modern electronics.en_US
dc.identifier.citationCherevko K. O. Boolean network optimization by stochastic rewiring / K. O. Cherevko // XII Всеукраїнська наукова конференцiя молодих математикiв, Київ, 9-11 травня 2024 р. : [збірник тез /оргком.: Глибовець А. М. та ін.] ; Нацiональний унiверситет Києво-Могилянська академiя" [та ін.]. - [Київ : б. в.], 2024. - C. 112-113.en_US
dc.identifier.urihttps://ekmair.ukma.edu.ua/handle/123456789/29761
dc.language.isoenen_US
dc.relation.sourceXII Всеукраїнська наукова конференцiя молодих математикiв: збірник тез доповідей, 9-11 травня 2024 рокуuk_UA
dc.statusfirst publisheden_US
dc.subjectlogic synthesisen_US
dc.subjectsilicon chipsen_US
dc.subjectnew area minimization algorithmsen_US
dc.subjectfaninen_US
dc.subjectconference abstractsen_US
dc.titleBoolean network optimization by stochastic rewiringen_US
dc.typeConference materialsuk_UA
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