Cherevko, Christina2024-06-122024-06-122024Cherevko K. O. Boolean network optimization by stochastic rewiring / K. O. Cherevko // XII Всеукраїнська наукова конференцiя молодих математикiв, Київ, 9-11 травня 2024 р. : [збірник тез /оргком.: Глибовець А. М. та ін.] ; Нацiональний унiверситет Києво-Могилянська академiя" [та ін.]. - [Київ : б. в.], 2024. - C. 112-113.https://ekmair.ukma.edu.ua/handle/123456789/29761In today’s rapidly evolving technological world, the demand for smaller yet more powerful computers is escalating at an unprecedented pace, driving a significant need for research in circuit optimizations. This surge in demand underscores the critical role of logic synthesis, which lies at the heart of digital circuit design. Logic synthesis serves as a pivotal stage in converting a high-level functionality description into an efficient hardware implementation. It is key to meeting the ever-increasing demands for miniaturization and performance enhancement in modern electronics.enlogic synthesissilicon chipsnew area minimization algorithmsfaninconference abstractsConference materials